1. Field of the Invention
Example embodiments relate to a memory device and a method of fabricating the same. More particularly, example embodiments relate to a nonvolatile memory device and a method of fabricating the same.
2. Description of the Related Art
A nonvolatile memory device, e.g., a read-only memory (ROM), an erasable and programmable read-only memory (EPROM), an electrically erasable and programmable read-only memory (EEPROM), and so forth, may retain stored data even without power supply. For example, the EEPROM, e.g., a flash memory, may electrically change stored data rapidly and easily, and may have a very high integration level, e.g., the flash memory may high integration level because of its small unit cell area. Accordingly, a market for, e.g., a flash memory device, has increased in recent years.
A conventional nonvolatile memory device may include a charge storage layer disposed between a control gate and a semiconductor substrate. A tunnel insulating layer may be disposed between the charge storage layer and the semiconductor substrate, and a dielectric layer may be disposed between the charge storage layer and the control gate. The nonvolatile memory device may store charges to represent data, e.g., logical “1” or logical “0,” depending on whether a charge is injected into the charge storage layer. The conventional nonvolatile memory device may be classified into a floating gate memory device and a charge trap memory device according to the type of its charge storage layer.
For example, a charge storage layer of the conventional floating gate flash memory device may include a floating gate, so the floating gate and the control gate may be sequentially stacked. A storage layer of the conventional charge trap flash memory device may have a MOSFET-like structure, i.e., may include a thin layer with a plurality of trap sites, and may be referred to as a charge trap layer. For example, the conventional charge trap flash memory device, e.g., SONOS or MONOS charge trap flash memory device, may include a silicon nitride layer as a charge trap layer.
An erase operation of the conventional memory device may be performed by applying an erase voltage, e.g., about (−15) V to about (−20) V, to the control gate. When the erase voltage is applied to the control gate in the conventional memory device, however, back tunneling may occur. For example, when erase voltage is applied to the control gate in the conventional memory device, electrons may move from the control gate toward the charge storage layer, and may remain in the dielectric layer between the control gate and the charge storage layer. Also, the back tunneling may occur even when the erase voltage is not applied to the control gate. Consequently, the time required to perform an erase operation of the conventional memory device may be increased. Further, data retention characteristics of the charge storage layer may be reduced, thereby decreasing reliability and operability of the memory device.